1. Field of the Invention
The present invention relates to a flip-flop control circuit for reducing low-frequency power supply noise, a processor incorporating the flip-flop control circuit, and a method for operating the processor.
2. Description of the Related Art
FIG. 5 is a diagram of a power supply circuit commonly used in a computer comprising a CMOS LSI. In FIG. 5, a wiring section 53 having resistance R and inductance L and a bypass capacitor 54 having capacitance C are interposed between the power supply unit 51 and the LSI 52. The R component is small and is unaffected by alternating current. For the L component, the wiring line is reduced in length and increased in thickness to reduce the effects of noise. For the C component, the capacitance of the electrolytic capacitor is increased to reduce the effects of noise. However, in this power supply circuit, there is a limit to how far the noise can be reduced because of limitations in component placement.
In computers comprising CMOS LSIs, there is a need to achieve faster operating speeds and lower power consumption. To address these requirements, Japanese Unexamined Patent Publication No. 8-286780 discloses a clock circuit, a processor, and a method for operating the processor, in which the computer is operated with low-frequency clock pulses in normal mode and during a finite period when switching from the normal mode to low power consumption mode and, after switching to the low power consumption mode, the computer is operated with high-frequency clock pulses.
It should also be noted that, in computers comprising CMOS LSIs, current consumption has increasing as their operating speeds and circuit densities increase.
However, in the clock circuit, the processor, and the method for operating the processor disclosed in the above-cited Japanese Unexamined Patent Publication No. 8-286780, if a clock pulse or reset signal is supplied at a time to flip-flops (FFs) in the LSI constituting the computer when determining the states of the FFS, there arises the problem that the consumption current of the LSI increases instantaneously, causing the computer to malfunction.
More specifically, when scanning FFS in the computer, or at the time of initial program load (IPL), gated clocks to be supplied to the flip-flops (FFs) in the LSI are started or stopped or resetting of the FFs is performed; at this time, a large transient current flows and, due to the inductance component of the power supply system, much AC power supply noise is caused, causing the supply voltage to fluctuate and adversely affecting the LSI, resulting in the problem that the computer malfunctions and the reliability is degraded.
The term xe2x80x9cscanxe2x80x9d here includes xe2x80x9cscan inxe2x80x9d where the outputs of all FFs in an LSI are set or reset, as when testing the LSI, and xe2x80x9cscan outxe2x80x9d where the outputs of the FFs are read out after the scan in. On the other hand, IPL refers to an initialization procedure in which a program for causing a computer""s operating system (OS) to commence operation is loaded from an external storage device into an internal memory of the computer by operating the console containing the computer""s CPU (central processing unit). As for the starting/stopping of gated clocks, enabling the supply of clock pulses to the FFs in the LSI is described as starting the gated clocks, while stopping the supply of clock pluses is described as stopping the gated clocks. Here, the FFs contained in the LSI include those used as latches.
It is, accordingly, an object of the present invention to resolve the above problems and provide a flip-flop control circuit for reducing low-frequency power supply noise, a processor incorporating the flip-flop control circuit, and a method for operating the processor.
According to a first embodiment of the invention that achieves the above object, there is provided a flip-flop control circuit, connected to a digital circuit having a plurality of flip-flops, for supplying the digital circuit with a signal that determines the states of the plurality of flip-flops, comprising: a clock generating circuit which generates a first clock pulse signal of a base frequency; a clock selecting circuit which receives the first clock pulse signal from the clock generating circuit, and which generates from the received first clock pulse signal a high-speed processing second clock pulse signal having a frequency higher than the base frequency, and outputs the first clock pulse signal or the second clock pulse signal in accordance with a control signal input thereto; a counter circuit which receives the first clock pulse signal or the second clock pulse signal from the clock selecting circuit, and which, when determining the states of the plurality of flip-flops, sets the control signal and starts counting the received clock pulse signal upon receiving an activation signal thereof, and clears the setting of the control signal upon expiration of a predetermined time; and a clock distributing circuit which receives the first clock pulse signal or the second clock pulse signal from the clock selecting circuit, and which distributes the received clock pulse signal to the plurality of flip-flops.
In the configuration of the first embodiment described above, after the activation signal is issued to determine the states of the plurality of flip-flops, the first clock pulse signal of the base frequency is supplied to the plurality of flip-flops until a predetermined time elapses and, after the predetermined time has elapsed, the high-speed processing second clock pulse signal having a frequency higher than the base frequency is supplied to the plurality of flip-flops; accordingly, since the high-frequency clock pulse signal is not supplied at one time to the plurality of flip-flops, an instantaneous increase in the current consumption is prevented and, as a result, low-frequency power supply noise is reduced.
According to a second embodiment of the invention that achieves the above object, there is provided a flip-flop control circuit, connected to a digital circuit having a plurality of flip-flops, for supplying the digital circuit with a signal that determines the states of the plurality of flip-flops, comprising: a clock generating circuit which generates a clock pulse signal of a base frequency; a counter circuit which receives the clock pulse signal from the clock generating circuit, and which, when determining the states of the plurality of flip-flops, sets a control signal and starts counting the received clock pulse signal upon receiving an activation signal thereof, and changes the setting of the control signal at each expiration of a predetermined time; and a clock distributing circuit which receives the clock pulse signal from the clock generating circuit, and which distributes the clock pulse signal to the plurality of flip-flops in sequence in accordance with the control signal.
In the configuration of the second embodiment described above, since, after issuing the activation signal to determine the states of the plurality of flip-flops, the clock pulse signal is distributed in sequence to the plurality of flip-flops as a predetermined time elapses, the clock pulse signal is not supplied at a time to the plurality of flip-flops; this prevents an instantaneous increase in the current consumption and, hence, reduces low-frequency power supply noise.
According to a third embodiment of the invention that achieves the above object, there is provided a flip-flop control circuit, connected to a digital circuit having a plurality of flip-flops, for supplying the digital circuit with a signal that determines the states of the plurality of flip-flops, comprising: a clock generating circuit which generates a clock pulse signal of a base frequency; a counter circuit which receives the clock pulse signal from the clock generating circuit, and which, when determining the states of the plurality of flip-flops, sets a control signal and starts counting the received clock pulse signal upon receiving an activation signal thereof, and changes the setting of the control signal at each expiration of a predetermined time; and a reset signal distributing circuit which distributes a reset signal to the plurality of flip-flops in sequence in accordance with the control signal.
In the configuration of the third embodiment described above, since, after issuing the activation signal to determine the states of the plurality of flip-flops, the reset signal is distributed in sequence to the plurality of flip-flops as a predetermined time elapses, the reset signal is not supplied at a time to the plurality of flip-flops; this prevents an instantaneous increase in the current consumption and, hence, reduces low-frequency power supply noise.
In the flip-flop control circuit according to the first, second, or third embodiment of the invention described above, the digital circuit comprises at least one LSI.
According to the invention that achieves the above object, there is also provided a processor comprising a flip-flop control circuit and a digital circuit according to the first, second, or third embodiment of the invention described above.
According to the invention that achieves the above object, there is also provided a method for operating a processor that comprises a plurality of flip-flops and a pulse generating circuit for generating a first clock pulse signal of a base frequency and a high-frequency processing second clock pulse signal having a frequency higher than the base frequency, the method comprising the steps of: when determining the states of the plurality of flip-flops, setting a control signal and starting counting either the first clock pulse signal or the second clock pulse signal upon receiving an activation signal thereof; clearing the setting of the control signal after a predetermined time has elapsed from the start of the counting; selecting either the first clock pulse signal or the second clock pulse signal in accordance with the control signal; and supplying the selected clock pulse signal to the plurality of flip-flops.
According to the invention that achieves the above object, there is also provided a method for operating a processor that comprises a plurality of flip-flops and a generating circuit for generating a clock pulse signal of a base frequency, the method comprising the steps of: when determining the states of the plurality of flip-flops, setting a control signal and starting counting the clock pulse signal upon receiving an activation signal thereof; after the start of the counting, changing the setting of the control signal at each expiration of a predetermined time; and distributing the clock pulse signal to the plurality of flip-flops in sequence in accordance with the control signal.
According to the invention that achieves the above object, there is also provided a method for operating a processor that comprises a plurality of flip-flops and a generating circuit for generating a clock pulse signal of a base frequency, the method comprising the steps of: when determining the states of the plurality of flip-flops, setting a control signal and starting counting the clock pulse signal upon receiving an activation signal thereof; after the start of the counting, changing the setting of the control signal at each expiration of a predetermined time; and distributing a reset signal to the plurality of flip-flops in sequence in accordance with the control signal.